True large-area image acquisition
The solution for chip design recovery, layout reconstruction, anti-counterfeiting, IP protection and brain mapping
For reverse engineering applications, cm²-large chip areas need to be scanned with nm resolution and excellent layer to layer accuracy (‘3D stitching’) for layout and schematic extraction.
CHIPSCANNER delivers the necessary performance for this demanding operation. CHIPSCANNER uniquely combines high-resolution electron optics, multiple, highly efficient electron detectors and most precise laser interferometer stage technology.
- Calibrated images
- Minimum image overlap
- Best layer to layer accuracy (Laser Interferometer Controlled Stage)
Calibrated image scans of up to 50,000 x 50,000 pixels reduce the number of images and seams still keeping smallest pixel sizes. Height-sensor-based focus correction, sample prelevelling technologies, built in temperature stabilization deliver homogenous large area image mosaics with smallest stitching errors and stable brightness/contrast values.
Depending on the selected stage travel range, several samples can be loaded and image mosaics can automatically be acquired without user interaction. Software tools are available to extract and optimize valuable GDSII-CAD data from the images for further processing.
- Chip design recovery
- Layout reconstruction
- Anti counterfeiting analysis
- IP protection
- Chip obsolescence management
- 30 kV
Inlense SE detector, Inlense BSE Detector
- 4“ - 8“
- Large Z travel